Shallow trench isolation (STI) technology is frequently used as an alternative to local oxidation of silicon (LOCOS) technology. STI technology generally involves forming a groove as a boundary between a device isolation layer and an active region. Self-aligned trench isolation techniques have been suggested in which a gate conductive layer is formed during the formation of a trench isolation layer.
Referring to FIG. 1, a typical flash memory device includes parallel device isolation layers 12 and 34 to define active regions. Control gate electrodes 42 cross the device isolation layers 12 and 34 in parallel. Floating gate electrodes 16a and 38a are formed on a substrate between the device isolation layers 12 and 34. The floating gate electrodes 16a and 38a are disposed between the control gate electrode 42 and the substrate. Edges of the floating gate electrodes 16a and 38a overlap the device isolation layers 12 and 34.
A method of fabricating a conventional flash memory device having a shallow trench isolation structure is described with reference to FIGS. 2-6.
Referring to FIG. 2, a buffer oxide layer 2 and a hard mask layer 4 are formed on a semiconductor substrate 1. The hard mask layer 4 may be, for example, silicone nitride. The buffer oxide layer 2 may buffer a stress applied to the substrate 1 by means of the hard mask layer 4.
Refining to FIG. 3, the hard mask layer 4 and the buffer oxide layer 2 are successively patterned to form a buffer oxide pattern 2a and a hard mask pattern 4a on the substrate 1. Using the hard mask pattern 4a as a mask, the substrate 1 is etched to form a trench 6 in the substrate 1. During this etch, the substrate 1 may be damaged, for example by defects in the sidewalls of the trench 6.
Referring to FIG. 4, in an attempt to cure the defects, the substrate 1 in the region of the trench 6 is annealed to form a trench oxide layer 10 on the inner sidewall of the trench 6. An insulating layer pattern 8 is formed on the trench oxide layer 10 to fill the trench 6 as well as a gap area between the hard mask patterns 4a. The insulating layer pattern 8 may be, for example, an oxide layer or a stack structure in which a silicon nitride layer and an oxide layer are sequentially stacked.
Referring to FIG. 5, the hard mask pattern 4a is removed, for example, by an isotropic etch technique using a phosphoric acid solution. The buffer oxide pattern 2a is removed, and then a sacrificial oxide layer is formed on the remaining structure to cure surface defects in the semiconductor 1 substrate between the insulating layer patterns 8. The sacrificial oxide layer is removed to form a device isolation pattern 12 filling the trench 6. A major top surface of the device isolation pattern 12 is even with or lower than the surface of the semiconductor substrate 1. When the buffer oxide pattern 2a and the sacrificial oxide layer are removed, the device isolation pattern 12 may be etched such that a dent is formed along an edge of the trench 6.
Referring to FIG. 6, a tunnel insulating layer and then a conductive layer are formed on an entire surface of the substrate 1 and the device isolation patterns 12. The tunnel insulation layer and the conductive layer are patterned to form a tunnel insulating layer pattern 14 and a conductive layer pattern 16 between the device isolation patterns 12. An edge of the conductive layer pattern 16 overlaps an upper side of the device isolation pattern 12. In a subsequent process, the conductive layer pattern 16 may be used as a floating gate pattern of the flash memory.
Referring, to FIG. 6, an electric field may concentrate on the conductive layer pattern 16, used as a floating gate pattern, along the edge of the trench 6. Consequently, a parasitic transistor may be formed along the edge of the trench 6 and may cause leakage current during memory operations. When a major top surface of the device isolation pattern 12 is higher than or even with a major top surface of the semiconductor substrate 1, a parasitic transistor may be formed by a control gate of the memory cell as well as the floating gate.
Methods of fabricating a flash memory device having a self-aligned shallow trench isolation structure are now described with reference to FIGS. 7-11.
Referring to FIG. 7, a tunnel insulating layer 20, a first polysilicon layer 22, and a silicon nitride layer 24 are sequentially formed on a semiconductor substrate 18.
Referring to FIG. 8, the silicon nitride layer 24, the first polysilicon layer 22, and the tunnel insulating layer 20 are successively patterned to form a tunnel insulating layer pattern 20a, a first polysilicon pattern 22a, and a silicon nitride pattern 24a on the semiconductor substrate 18. Using the silicon nitride pattern 24a as a mask, the substrate 18 is etched to form a trench 26.
Referring to FIG. 9, in order to cure defects that may occur in an inner sidewall of the trench 26, the substrate 18 is annealed to form a trench oxide layer 28 on the inner sidewall of the trench 26. During this annealing step, oxidation can occur along sidewalls of the first polysilicon patterns 22a and along where the first polysilicon patterns 22a and the semiconductor substrate 18 are in contact with edges of the tunnel insulating layer patterns 20a. Consequently, an undesirable bird's beak may occur at the edge of the tunnel insulating layer 20a. A trap density of the bird's beak may become large as write and erase operations are repetitively performed. Consequently, the bird's beak may deteriorate the data retention and/or life of the flash memory device.
An insulating layer pattern 30 is formed to fill the trench 26 on the trench oxide layer 28 and a gap area between the silicon nitride patterns 24a. 
Referring to FIG. 10, the silicon nitride pattern 24a is removed to expose the first polysilicon pattern 22a. A device isolation pattern 34 is formed from the insulating layer pattern 30 in the trench 28 and extends along the sidewalls of the first polysilicon patterns 22a and the trench oxide layer 28. A second polysilicon layer is formed on an entire surface of the substrate 18, and then patterned to form a second polysilicon pattern 36 on the first polysilicon pattern 22a. 
Referring to FIG. 11, an integrate dielectric 40 is formed on an entire surface of the substrate 18, including on the second polysilicon pattern 36. A control gate conductive layer 42 is formed on an entire surface of the integrate dielectric 40. The integrate dielectric 40 may be, for example, ONO (oxide/nitride/oxide) and the control gate conductive layer 42 may be polysilicon or metal polycide.
A conventional flash memory device having a self-aligned shallow trench isolation structure is illustrated in FIGS. 12-13.
Referring to FIGS. 11-12, the control gate conductive layer 42, the integrate dielectric 40, the second polysilicon pattern 36, and the first polysilicon pattern 22a are successively patterned to form an integrate dielectric pattern 40a and a control gate electrode 42a which are sequentially stacked to cross over the device isolation pattern 34, and to form a floating gate pattern 38 between the integrate dielectric pattern 40a and the tunnel insulating layer pattern 30a. The tunnel insulating layer pattern 20a between the control gate electrodes 42a may be patterned or unpatterned.
In the conventional flash memory device with the self-aligned trench isolation structure, the device isolation pattern 34 protrudes beyond a top surface of the semiconductor substrate 18, as shown in FIG. 12, and has a vertical sidewall. A stringer 44 may remain at a base of the protruding sidewall of the device isolation pattern 34 when the first and second polysilicon patterns 22a and 36 are patterned in order to form the floating gate pattern 38. The stringers 44, when present, may short-circuit the adjacent floating gate patterns 38. An overetch, using an isotropic etch process, is sometimes performed, using a wet etch or a dry etch after the floating gate pattern 38 is formed, to remove the stringers 44. An undercut 44 may result along a lower sidewall of the floating gate pattern 38, as shown in FIG. 13, so that a short channel effect may occur for the cell transistor and the gate line width in a cell array may be less uniform, which may result in increased variation in the cell characteristics. Moreover, following formation of a gate line, a large amount of oxygen atoms may be diffused through the bird's beak 32 (see FIG. 10) in a thermal oxidation process for curing etch damage, which may increase the thickness of the floating gate pattern 38. When the thickness of the floating gate pattern 38 is increased, a corresponding increase in parasitic capacitance may occur between adjacent floating gates patterns 38. The parasitic capacitance may result in variations of the threshold voltage of the flash memory cell.